Provide an opportunity to improve the knowledge of the VHDL language and, more importantly, to design a digital “system”. You will be expected to learn to: a) implement digital system design in VHDL code; b) synthesise and download it to the target hardware;which would be simulated since there is no physical basys 3 fpga hardware. c) test, debug, and verify that the design meets the specifications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx Artix 7 FPGA) in order to implement a design that meets the specifications (below). Your design will be varied by testbenches in Vivado simulator. You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of non-standard packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED) and BUFFER ports is forbidden, while the use of INOUT ports is accepted only when strictly necessary.
You are supposed to gain familiarity with VHDL coding during the supporting CE869 lectures videos and through self-study hours, also with the help of the recommended textbooks or any other book about VHDL. You are expected to work on this assignment mostly during your own hours. Your design project should be stored under the revision control repository that was assigned to you at the beginning of the course. You are supposed to commit often and describe your progress in the commit messages. In order to promote a learning scheme that values the learning process in addition to the submitted final design, your weekly progress (as traced back by the commit logs) will contribute to your assignment mark.

Design specifications
Your task for this assignment is to implement a 16 bit CPU. To make the assignment feasible within the time frame available for this module, the type of CPU will be fairly simple. In particular, the “program sequencing/control flow instruction” datapath can be modelled after the one on the left of Figure 1, while the “arithmetic/logic instruction” datapath can follow a structure like the one on the right in the same figure. Please notice that when RAE and/or RBE are low, the corresponding output(s) will simply match the input “I” to the register file. The opcodes for the instructions that the CPU is required to implement are given in Table 1. You are also required to implement a decode unit in control unit to interpret the ‘Affects’ and control signals from the output of each instruction.
To test your CPU, you will design a main entity that instantiates the CPU and connects it to the Basys3 peripherals. The sixteen switches of the Basys3 board will represent the input to the CPU while its output will be shown as hexadecimal number in the four digits of the 7-segment display. The central button will be used as reset signal to the CPU.
To test the CPU you will be asked to code two programs in the assembly and machine languages of the CPU, implementing the following tasks (A VHDL testbench should be used to test the functions of the CPU.):
A. Given a nonzero number N as input, output the sum of the natural numbers less than N ;
B. Given a number N as input, output “N modulo 13” (i.e. the remainder of the integer division between N and 13);
These design specifications should be interpreted as guidelines and should not constrain you from improving the CPU by doing modifications that you think would result in a better “product”. The test programs above, though, should be implemented using only the instructions in Table 1. You are welcome to implement more elaborated programs to test the capabilities and the limitations of the CPU.

Sample Solution

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