Design a 3-bit synchronous up counter which starts to count from 0 (000 binary)

Design a 3-bit synchronous up counter which starts to count from 0 (000 binary) and increments upwards to 7 (111 binary) and then starts new counting cycle by getting reset. Any preferred components (flip-flops: SR, JK, T or D and combinational circuits such as decoders, MUXs, etc.) could be used . Allow some time for each digit to display by adjusting the clock accordingly. This is an individual or group project (maximum of 2 students) and will be presented in both hardware using the minimum number of IC packages and multisim. Please submit a final report following the same guidelines as lab reports. Final report is due on Friday, May 6 by noon. Project demonstrations will be held in VET 174. Please notify me as soon as you are ready via email.